1. Field of the Invention
The present invention relates to a packet error detecting device for detecting the existence of error in the packet data transferred by the packet switching in a DMA transfer.
2. Description of the Related Art
Various devices for detecting a packet error have been proposed in order to improve reliability in the data transfer by packet switching for transferring data in every packet. Packet error detection in the packet switching in the DMA transfer has been generally performed by software without using any special hardware.
As the conventional packet error detecting devices, there are disclosed, for example, Japanese Patent Publication Laid-Open (Kokai) No. Heisei 2-41050 "Communication System", No. 2-119319 "CRC Code Generation Circuit", No. Heisei 3-204257 "Node Station", No. Heisei 4-107014 "Error Detection Method in CRC", No. Heisei 5-35616 "Data Transfer System" and No. Heisei 5-75577 "Data Error Detecting Device".
The Patent Publication No. Heisei 2-41050 "Communication System" discloses a communication system having sending units for sending the send data divided into a plurality of packets with detection codes respectively attached thereto and receiving units for receiving the packet data and instructing the sending units to resend only the packet having an error detected by use of the error detection code, wherein packet error detection can be performed in the receiving units.
The Patent Publication No. Heisei 2-119319 "CRC Code Generation Circuit" discloses a CRC code generation circuit for generating CRC code for use in packet error detection in the communication units of multi-lines, the CRC code generation circuit comprising a CRC operation circuit for performing CRC operation by entering the data string of multi-frame with a plurality of lines multiplexed, a flip-flop for storing the CRC operation results temporarily, a shift register for storing each final value of operation in each multi-frame line in the CRC operation results, and selecting units for selecting the content stored in the shift register at the first bit at the starting of the operation of each line and selecting the content stored in the flip-flop at another timing as the CRC operation value one bit ahead.
The Patent Publication No. Heisei 3-204257 "Node Station" discloses a node station of a data communication system for performing communication by use of a packet frame having frame check sequence over a loop-shaped network of signal transfers in a single direction, the node station comprising frame check units for detecting any error of frames of the whole packets relayed or received by use of the frame check sequence and storing units for storing the existence of the error if the frame check units detects an error, thereby enabling it to take away easily the channel having an error.
The Patent Publication No. Heisei 4-107014 "Error Detection Method in CRC" discloses a CRC error detection method of operation using a remainder obtained by dividing the code polynomial for N bits by the generating function as the redundancy check code for error detection, in which operation is performed in every n bits (n&gt;1), thereby shortening the operation time.
The Patent Publication No. Heisei 5-35616 "Data Transfer System" discloses a data transfer system, in which the parity code and the CRC code are attached to the send data, so to transfer the data to the bus, the parity check and the CRC check are performed in a receiving device having received the data, and only when no error is detected, the data is supplied to the hardware, thereby detecting the occurrence of a bus error accurately and preventing the transfer of the wrong data into the hardware at the occurrence of a bus error.
The Patent Publication No. Heisei 5-75577 "Data Error Detecting Device" discloses a data error detecting device capable of real-time processing and eliminating a buffer memory for storing data temporarily, the device comprising a CRC operation unit for supplying a remainder obtained by dividing the input data by the generating function, as the operation data, and an error analytical unit for converting the operation data, upon receipt of it, into the bit error data corresponding to the operation data, so to supply the data.
These conventional packet error detecting devices, however, are not designed to be used in the DMA transfer and these techniques cannot be used to detect a packet error in the DMA transfer as they are.
The Patent Publication No. Heisei 2-181248 "DMA System" discloses a DMA system having a descriptor pointer register sequentially incremented for storing a head pointer of a descriptor table corresponding to a receive frame, a store descriptor pointer register for storing a head descriptor pointer of a descriptor table corresponding to a receive frame, and a status control unit for detecting an error of a receive frame, the system improving the processing speed of the DMA transfer by, if detecting an error in a receive frame, storing the head pointer of the receive frame stored in the store descriptor pointer register and transferring the next receive frame to the buffer according to the same content of the descriptor table. This publication, however, includes no description about the technique of detecting a packet error.
As mentioned above, the conventional method of detecting a packet error in the DMA transfer has a defect that the processing speed is slow because the packet error detection is performed by the software operation.